System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network

A system comprising:

• a first, interconnection network;
• a processor coupled to the interconnection network;
• a host interface coupled to the interconnection network;
• and
• at least one configurable circuit cluster coupled to the interconnection network, the configurable circuit cluster comprising:
• a plurality of configurable circuits arranged in an array, each configurable circuit, comprising:
• a configurable computation circuit;
• a first memory circuit coupled to the configurable computation circuit;
• a plurality of synchronous network inputs and outputs coupled to the configurable computation circuit;
• an asynchronous network input queue and an asynchronous network output queue;
• a second, configuration memory circuit coupled to the configurable computation circuit, to the control circuitry, to the synchronous network inputs, and to the synchronous network outputs, the second, configuration memory comprising:
• a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit;
• and
• a second, instruction and instruction index memory storing:
• a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input of the synchronous network inputs, for selection of a current data path configuration instruction for the configurable computation circuit, and for selection of a next data path instruction or next data path instruction index for a next configurable computation circuit;
• and
• a control circuit coupled to the configurable computation circuit, the control circuit comprising:
• a memory control circuit;
• a plurality of control registers, wherein the plurality of control registers store a completion table having a first, data completion count;
• and
• a thread control circuit adapted to queue a thread for execution.

A system comprising:

• a first, interconnection network;
• a host interface coupled to the interconnection network;
• at least one configurable circuit cluster coupled to the interconnection network, the configurable circuit cluster comprising a plurality of configurable circuits arranged in an array;
• and
• a processor coupled to the interconnection network, the processor comprising:
• a processor core adapted to execute a plurality of instructions;
• and
• a core control circuit coupled to the processor core, the core control circuit comprising:
• an interconnection network interface coupleable to an interconnection network to receive a work descriptor data packet, to decode the received work descriptor data packet into an execution thread having an initial program count and any received argument;
• a thread control memory coupled to the interconnection network interface and comprising a plurality of registers, the plurality of registers comprising a thread identifier pool register storing a plurality of thread identifiers, a thread state register, a program count register storing the received program count, a data cache, and a general purpose register storing the received argument;
• an execution queue coupled to the thread control memory;
• a control logic and thread selection circuit coupled to the execution queue and to the thread control memory, the control logic and thread selection circuit adapted to assign an available thread identifier to the execution thread, to place the thread identifier in the execution queue, to select the thread identifier for execution, to access the thread control memory using the thread identifier as an index to select the initial program count for the execution thread;
• and
• an instruction cache coupled to the processor core and to the control logic and thread selection circuit to receive the initial program count and provide to the processor core a corresponding instruction for execution, of the plurality of instructions.