US 2019/0171601 A1 · MECHANISMS FOR FPGA CHAINING AND UNIFIED FPGA VIEWS TO COMPOSED SYSTEM HOSTS

Abstract

Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.

Claims28

Dependent claims

A computer-implemented method, comprising:

linking a plurality of Field Programmable Gate Arrays (FPGA) in communication to form a chain of FPGAs, the plurality of FPGAs including an FPGA that is coupled to a processor in a compute node, each of the plurality of FPGAs having respective a size;
and
exposing the chain of FPGAs to a to a hypervisor, an operating system virtualization layer, or to an operating system hosted by the compute node as a virtual monolithic FPGA have a size that is an aggregate of the individual sizes of the FPGAs in the chain of FPGAs.

A method implemented by components in a plurality of pooled system drawers installed in a rack, the pooled system drawers including one or more pooled compute drawers and one or more pooled Field Programmable Gate Array (FPGA) drawers, comprising:

for each of the one or more pooled compute drawers installed in a rack,
enumerating Field Programmable Gate Array (FPGA) devices that are associated with compute nodes installed in the pooled compute drawer;
for each of the one or more pooled FPGA drawers installed in a rack,
enumerating FPGAs installed in the pooled FPGA drawer;
identifying chainable FPGAs among the FPGAs that are enumerated associated with the compute nodes installed in the one or more pooled compute drawers and the FPGAs that are enumerated for the one or more pooled FPGA drawers;
identifying intra-drawer FPGA chaining mechanisms for chaining chainable FPGAs within the one or more pooled compute drawers and the one or more pooled FPGA drawers;
and
identifying inter-drawer FPGA chaining mechanisms for chaining chainable FPGAs located in separate pooled system drawers;
and
composing a unified view of the FPGAs for the rack, the unified view identifying a location and at least one of a size and type of each FPGA, whether the FPGA is a chainable FPGA, and a chaining mechanism for each chainable FPGA.

7 more elements

Dependencies are inferred from the claim text.

Mechanisms for fpga chaining and unified fpga views to composed system hosts

Life of this patent

Mechanisms for fpga chaining and unified fpga views to composed system hosts

Life of this patent

Abstract

Claims28