Hybrid architecture for signal processing and signal processing accelerator
AssigneeAltera Corporation
InventorSteven Perry
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Abstract
Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.
Claims36
An integrated circuit system, comprising:
- programmable logic circuitry in a first region of the integrated circuit system;
- an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function;
- and
- an interconnect network that enables communication between ISA-based signal processors of the array of ISA-based signal processors.
An integrated circuit system, comprising:
- programmable logic circuitry in a first region of the integrated circuit system;
- an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region;
- and
- an interconnect network that communicatively connects a first ISA-based signal processor of the array of ISA-based signal processors to a second ISA-based signal processor of the array of ISA-based signal processors to skip a third ISA-based signal processor located between the first ISA-based signal processor and the second ISA-based signal processor in the array of ISA-based signal processors.
The integrated circuit system of 12, wherein the array of ISA-based signal processors comprises at least a first row, a second row, and a third row of ISA-based signal processors, and a first column, a second column, and a third column of ISA-based signal processors.
The integrated circuit system of 12, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function.
The integrated circuit system of 14, wherein the filtering function comprises digital pre-distortion (DPD) processing.
An integrated circuit system, comprising:
- programmable logic circuitry in a first region of the integrated circuit system;
- an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function;
- and
- a hardened processing system that controls and monitors the array of ISA-based signal processors.
The integrated circuit system of 16, wherein the hardened processing system controls and monitors the array of ISA-based signal processors by updating contents of and configuring the array of ISA-based signal processors.
An integrated circuit system, comprising:
- field programmable gate array (FPGA) circuitry in a first region of the integrated circuit system;
- an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region;
- and
- an interconnect network that communicatively connects a first ISA-based signal processor of the array of ISA-based signal processors directly to stream data to a second ISA-based signal processor of the array of ISA-based signal processors.
The integrated circuit system of 20, wherein the array of ISA-based signal processors is programmable to perform a filtering function.
The integrated circuit system of 24, wherein the filtering function comprises digital pre-distortion (DPD) processing.
A method, comprising:
- receiving input data at an array of instruction set architecture (ISA)-based signal processors in a first region of an integrated circuit separate from a second region comprising programmable logic circuitry of the integrated circuit, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function;
- and
- routing communication between at least a portion of the array of ISA-based signal processors via an interconnect network.
A method comprising:
- facilitating a first portion of a filtering function using a field-programmable gate array of an integrated circuit device;
- and
- performing a second portion of a filtering function using an array of instruction set architecture (ISA)-based signal processors of the integrated circuit device, wherein performing the second portion of the filtering function comprises:
- receiving, at the array of ISA-based signal processors, at least one instruction to perform the second portion of the filtering function;
- and
- generating output data based at least in part on the at least one instruction.
Dependencies are inferred from the claim text.