Clock line driving for single-cycle data over clock signaling and pre-emption request in a multi-drop bus

An apparatus, comprising:

• a bus interface configured to couple the apparatus to a serial bus, the bus interface including a line driver adapted to drive a first line of the serial bus;
• and
• a controller configured to:
• provide a clock signal on the first line of the serial bus;
• transmit data on a second line of the serial bus in accordance with timing provided by the clock signal;
• cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line;
• detect a first pulse on the clock signal while the line driver is in the high impedance state;
• cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, wherein the first edge and the second edge comprise transitions in opposite directions;
• and
• initiate bus arbitration after detecting the first pulse.

A processor-readable storage medium comprising code for:

• providing a clock signal on a first line of a serial bus;
• transmitting data on a second line of the serial bus in accordance with timing provided by the clock signal;
• causing a driver of the first line of the serial bus to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line;
• detecting a first pulse on the clock signal while the driver of the first line is in the high impedance state;
• causing the driver of the first line of the serial bus to exit the high impedance state prior to transmitting a second edge in the clock signal, wherein the first edge and the second edge comprise transitions in opposite directions;
• and
• initiating bus arbitration after detecting the first pulse.

A method for transmitting data over a serial bus comprising:

• receiving a clock signal from a first line of the serial bus;
• receiving data from a second line of the serial bus in accordance with timing provided by the clock signal;
• transmitting a pulse on the clock signal while the clock signal is in a first signaling state;
• and
• participating in bus arbitration after transmitting the pulse on the clock signal.