Parallel fault simulator with back propagation enhancement

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• injecting a fault at a first node of a simulated integrated circuit design having been input with a stimulus vector, wherein alarm logic is configured to trigger indicating a detection of the injected fault;
• identifying which intermediate nodes of the simulated integrated circuit, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger;
• and
• generating a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.

A system comprising:

• a memory system configured to store computer-executable instructions;
• and
• a computing system, in response to execution of the computer-executable instructions, is configured to:
• inject a fault at a first node of a simulated integrated circuit design having been input with a stimulus vector, wherein alarm logic is configured to trigger indicating a detection of the injected fault,
• identify which intermediate nodes of the simulated integrated circuit, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger, and
• generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.