Logic buffer for hitless single event upset handling

A system for handling a single event upset (SEU), the system comprising:

• a monitored device comprising static random access memory (SRAM) comprising stored logic;
• an initial state change device operatively connected to the monitored device, comprising a first input and a first output, and configured to receive a first data from the monitored device at the first input;
• a state hold device comprising a second input and a second output, wherein the second input is operatively connected to the first output;
• a delay counter configured to count a delay period;
• the state comparator operatively connected to the first input, the initial state change device enable input of the initial state change device, and the delay counter, and configured to:
• detect, based receiving the first data, a first state change;
• assert, based on detecting the first state change, an initial state change device enable signal for the initial state change device to transfer the first data from the first input to the first output;
• and
• trigger, based on detecting the first state change, the delay counter to count the delay period;
• a validation engine operatively connected to the monitored device, the delay counter, and the state hold device, and configured to:
• make a first determination that the delay period counted by the delay counter expired without receipt, by the validation engine, of an error detection signal from the monitored device;
• and
• based on the first determination that no error detection signal was received during the delay period, assert a state hold device enable signal to allow the first data to pass from the second input to the second output of the state hold device.

A system for handling a single event upset (SEU), the system comprising:

• a monitored device comprising static random access memory (SRAM) comprising stored logic;
• an initial state change device operatively connected to the monitored device, comprising a first input and a first output, and configured to receive a first data from the monitored device at the first input;
• a state hold device comprising a second input and a second output, wherein the second input is operatively connected to the first output;
• a delay counter configured to:
• receive a first load signal from the monitored device when a first state change occurs;
• and
• count a delay period after receiving the first load signal;
• a validation engine operatively connected to the monitored device, the delay counter, and the state hold device, and configured to:
• make a first determination that the delay period counted by the delay counter expired without receipt, by the validation engine, of an error detection signal from the monitored device;
• and
• based on the first determination, assert a state hold device enable signal to allow the first data to pass from the second input to the second output of the state hold device.