Management controller-based solution for processor ras in smi-free environment

A computing platform, comprising:

• a processor, including one or more memory controllers;
• for each of the memory controllers, one or more system memory device coupled to that memory controller;
• a platform management controller (PMC), either communicatively coupled to the processor or integrated on the processor,
• a firmware device, coupled to the processor having system firmware installed therein;
• and
• a plurality of Reliability, Availability, and Serviceability (RAS) data sources, including at least one of,
• RAS data sources on the processor;
• and
• RAS data sources on components coupled to the processor,
• wherein the platform is configured, upon operation, to,
• host an operating system, the operating system either running on platform hardware or running in a virtual machine running on the platform;
• map physical memory addresses for at least one system memory device to a virtual memory space in which an operating system is run,
• collect RAS data from at least a portion of the plurality of RAS data sources using the PMC;
• enable the operating system to access the RAS data collected by the PMC.

An apparatus comprising:

• an input-output (IO) interface;
• and
• on-board memory,
• wherein the apparatus is configured to be communicatively coupled to a processor in a computing platform via the IO interface, the processor including one or more memory controllers to which one or more system memory devices are coupled, the computing platform having a plurality of Reliability, Availability, and Serviceability (RAS) data sources, including at least one of,
• RAS data sources on the processor;
• and
• RAS data sources on components coupled to the processor,
• wherein the apparatus is configured to, when communicatively coupled to the processor and when the computing platform is operating, at least one of,
• collect RAS data from one or more of the plurality of RAS data sources and store the RAS data that is collected in the on-board memory;
• and
• receive RAS data relating to RAS events from one or more of the plurality of RAS data sources and store the RAS data that is received in the on-board memory.