Processing core having shared front end unit

A method performed by a processor, comprising:

• performing at least one of a) and b) below with same logic circuitry of a processing core of said processor:
• a) fetching first and second instructions of two different threads;
• b) decoding said first and second instructions into respective units of microcode, input operand address information and resultant address information;
• dispatching said respective units of microcode and address information to two different processing units;
• and,
• at each processing unit performing the following for its respective one of said two threads:
• storing its respective thread's microcode;
• fetching input operand data with a received input operand address;
• executing received microcode upon said fetched input operand with functional unit circuitry that is part of a set of functional units that support a complete general purpose instruction set.

A processor, comprising:

• at least two processing cores each having:
• a front end unit to fetch all respective instructions of all threads processed by its processing core and decode said instructions into respective micro-code and input operand and resultant addresses of said instructions;
• said front end unit coupled to all general purpose processing units of its processing core, each of said processing units to be assigned at least one of said threads, each processing unit coupled to said front end unit to receive microcode and input operand and resultant addresses of its assigned at least one of said threads, each of said plurality of processing units comprising:
• i) at least one set of functional units corresponding to a complete general purpose instruction set offered by said processor, said at least one set of functional units to execute its respective processing unit's received microcode;
• ii) registers coupled to said at least one set of functional units to store operands and resultants of said received microcode;
• iii) data fetch circuitry to fetch input operands for said at least one functional units' execution of said received microcode;
• an interconnection network coupled to said plurality of processing units;
• a last level cache coupled to said interconnection network.