Skip ahead allocation and retirement in dynamic binary translation based out-of-order processors

A system comprising:

• a memory;
• and
• a processor, communicatively coupled to the memory, comprising:
• a binary translator circuit to convert an instruction stream into an annotated instruction stream comprising an independent code tag identifying an independent code segment and a dependent code tag identifying a dependent code segment;
• a front end circuit to:
• receive the annotated instruction stream in order;
• responsive to identifying the independent code tag in the annotated instruction stream, allocate instructions of the independent code segment associated with the independent code tag into a buffer;
• and
• responsive to identifying the dependent code tag, reserve a space for the dependent code segment associated with the dependent code tag;
• and
• an instruction execution circuit to execute the independent code segment prior to executing the dependent code segment.

A method comprising:

• converting, by a binary translator of a processor, an instruction stream into an annotated instruction stream comprising an independent code tag identifying an independent code segment and a dependent code tag identifying a dependent code segment, wherein execution of the dependent code segment depends on a result of execution of the independent code segment;
• responsive to identifying the independent code tag in the annotated instruction stream, allocating, by the processor, instructions of the independent code segment associated with the independent code tag into a buffer;
• responsive to identifying the dependent code tag, reserving, by the processor, a space for the dependent code segment associated with the dependent code tag;
• and
• executing, by the processor, the independent code segment prior to executing the dependent code segment.