Programmable matrix processing engine

A matrix processing circuit, comprising:

• a matrix routine memory comprising circuitry to store a plurality of programmable matrix routines, wherein each of the plurality of programmable matrix routines comprises instructions for performing a corresponding matrix operation of a plurality of matrix operations;
• one or more matrix processing units comprising circuitry to perform matrix computations;
• and
• a controller comprising circuitry to:
• receive a command to perform a particular matrix operation of the plurality of matrix operations;
• identify a programmable matrix routine corresponding to the particular matrix operation, wherein the programmable matrix routine is identified from the plurality of programmable matrix routines;
• receive the programmable matrix routine from the matrix routine memory;
• execute the programmable matrix routine, wherein one or more matrix computations associated with execution of the programmable matrix routine are performed using the one or more matrix processing units;
• and
• determine a result of the particular matrix operation, wherein the result is determined based on execution of the programmable matrix routine.

A system, comprising:

• a processor to execute an application, wherein execution of the application comprises a plurality of matrix operations;
• and
• matrix processing circuitry to perform the plurality of matrix operations, wherein the matrix processing circuitry comprises:
• a matrix routine memory comprising circuitry to store a plurality of programmable matrix routines, wherein each of the plurality of programmable matrix routines comprises instructions for performing a corresponding matrix operation of the plurality of matrix operations;
• one or more matrix processing clusters, wherein each of the one or more matrix processing clusters comprises a plurality of matrix processing units, wherein the plurality of matrix processing units comprise circuitry to perform matrix computations;
• and
• a controller comprising circuitry to:
• receive a command to perform a particular matrix operation of the plurality of matrix operations;
• identify a programmable matrix routine corresponding to the particular matrix operation, wherein the programmable matrix routine is identified from the plurality of programmable matrix routines;
• receive the programmable matrix routine from the matrix routine memory;
• distribute execution of the programmable matrix routine across the one or more matrix processing clusters;
• and
• determine a result of the particular matrix operation, wherein the result is determined based on execution of the programmable matrix routine.

At least one non-transitory machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to:

• receive a command to perform a particular matrix operation of a plurality of matrix operations;
• identify a programmable matrix routine corresponding to the particular matrix operation, wherein the programmable matrix routine is identified from a plurality of programmable matrix routines, wherein each of the plurality of programmable matrix routines comprises programmable instructions for performing a corresponding matrix operation of the plurality of matrix operations;
• receive the programmable matrix routine from a matrix routine memory, wherein the plurality of programmable matrix routines are stored on the matrix routine memory;
• execute the programmable matrix routine, wherein one or more matrix computations associated with execution of the programmable matrix routine are performed using one or more matrix processing units, wherein the one or more matrix processing units comprise circuitry to perform matrix computations;
• and
• determine a result of the particular matrix operation, wherein the result is determined based on execution of the programmable matrix routine.

A method, comprising:

• receiving a command to perform a particular matrix operation of a plurality of matrix operations;
• identifying a programmable matrix routine corresponding to the particular matrix operation, wherein the programmable matrix routine is identified from a plurality of programmable matrix routines, wherein each of the plurality of programmable matrix routines comprises programmable instructions for performing a corresponding matrix operation of the plurality of matrix operations;
• receiving the programmable matrix routine from a matrix routine memory, wherein the plurality of programmable matrix routines are stored on the matrix routine memory;
• executing the programmable matrix routine, wherein one or more matrix computations associated with execution of the programmable matrix routine are performed using one or more matrix processing units, wherein the one or more matrix processing units comprise circuitry to perform matrix computations;
• and
• determining a result of the particular matrix operation, wherein the result is determined based on execution of the programmable matrix routine.