Modulo Hardware Generator

A modulo hardware generation engine configured to generate a hardware design to calculate a modulo value for any integer input value in a target input range with respect to a constant value d, the hardware design comprising one or more range reduction stages, the engine comprising:

• a plurality of range reduction modules, each range reduction module configured to generate a hardware design component to map an input range using one of a plurality of modulo preserving range reduction methods;
• a synthesis module configured to generate one or more synthesis metrics for a hardware design component, the one or more synthesis metrics providing an indication of a quality of a synthesized version of the hardware design component;
• decision logic in communication with the plurality of range reduction modules and the synthesis module, the decision logic configured to:
• (a) generate at least one hardware design component to map a desired input range to a target output range using each of the plurality of range reduction modules;
• (b) obtain one or more synthesis metrics for each of the hardware design components from the synthesis module;
• (c) select one of the hardware design components as an optimum hardware design component for the desired input range based on the synthesis metrics;
• and
• (d) expand the desired input range and repeat (a) to (d) until an input range of the optimum hardware design component comprises the target input range.

A non-transitory computer readable storage medium having stored thereon a hardware design to calculate a modulo value that was generated according to a computer-implemented method that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to generate a manifestation of an integrated circuit to calculate the modulo value, wherein the modulo value is calculated for any integer input value in a target input range with respect to a constant value d, the hardware design comprising one or more range reduction stages, and the computer-implemented method comprising:

• (a) generating at least one hardware design component to map a desired input range to a target output range using each of a plurality of modulo preserving range reduction methods;
• (b) synthesizing each of the hardware design components;
• (c) selecting one of the hardware design components as an optimum hardware design component for the desired input range based on the synthesis;
• and
• (d) expanding the desired input range and repeating (a) to (d) until an input range of the optimum hardware design component comprises the target input range.