Memory device, memory controller, and storage device including the same

A controller comprising:

• a control logic circuit configured to output one or more control signals to a memory device comprising a plurality of memory chips;
• a packet interface configured to receive a packet comprising status information and a chip number corresponding to at least one of the plurality of memory chips from the memory device;
• and
• a background processor comprising a packet receiver configured to receive the packet from the packet interface and to output status information about at least one of the plurality of memory chips to the control logic circuit based on the packet.

A memory device comprising:

• a plurality of memory chips distinguished from one another by their corresponding chip numbers;
• and
• a monitor circuit comprising a plurality of first connection terminals electrically connected to the plurality of memory chips in one-to-one correspondence and a packet generator configured to receive status information about each of the plurality of memory chips from the plurality of first connection terminals,
• wherein the packet generator is further configured to generate a plurality of packets each comprising a chip number and the status information, and
• wherein the monitor circuit is configured to output the plurality of packets based on a predetermined condition.