Wear Leveling in Solid State Drives
AssigneeMicron Technology, Inc.
InventorZoltan Szubbocsev
Life of this patent
Estimating the term…
Abstract
A computer storage device having: a host interface; a controller; non-volatile storage media having memory units of different types and having different program erase budgets; and firmware. The firmware instructs the controller to: generate an address map mapping logical addresses to physical addresses of the memory units the different types; and adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.
Claims20
A solid state drive, comprising:
- a host interface;
- a controller;
- a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively;
- and
- firmware containing instructions configured to instruct the controller to:
- generate an address map mapping logical addresses to physical addresses of the memory units the different types;
- and
- adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.
A method implemented in a solid state drive, the method comprising:
- providing a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively;
- generating an address map mapping logical addresses to physical addresses of the memory units the different types;
- and
- adjusting the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.
A non-transitory computer storage medium storing instructions which, when executed on a solid state drive, cause the solid state drive to perform a method, the method comprising:
- providing data access to a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively;
- generating an address map mapping logical addresses to physical addresses of the memory units the different types;
- and
- adjusting the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.
Dependencies are inferred from the claim text.