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US 2019/0171359 A1Published application
Memory module and memory system including the memory module
AssigneeSK hynix Inc.
InventorsDong Uk LEE, Kyung Whan KIM
Life of this patent
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Abstract
A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.
Claims16
A memory system comprising:
- a controller;
- and
- a plurality of memory modules,
- wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common,
- wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip,
- wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.
3 more elements
A memory system comprising:
- a controller;
- and
- a plurality of memory modules,
- wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common,
- wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip,
- wherein memory chips in a column direction among the plurality of memory chips in the plurality of memory modules are divided into ranks in single column units or in plural column units
- wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus,
- wherein a data input and output of the plurality of memory modules is performed in rank units in the single channel manner.
5 more elements
Dependencies are inferred from the claim text.