Radio-frequency loss reduction in photonic circuits
AssigneeAurrion, Inc.
InventorsJohn Parker, Gregory Alan Fish, Brian R. Koch
Life of this patent
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Abstract
In photonic integrated circuits implemented in silicon-on-insulator substrates, non-conductive channels formed, in accordance with various embodiments, in the silicon device layer and/or the silicon handle of the substrate in regions underneath radio-frequency transmission lines of photonic devices can provide breaks in parasitic conductive layers of the substrate, thereby reducing radio-frequency substrate losses.
Claims20
A photonic integrated circuit (PIC) comprising:
- a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, a silicon device layer disposed on top of the buried oxide layer;
- a cladding layer disposed on top of the silicon device layer;
- a waveguide formed within at least one of the silicon device layer or the cladding layer;
- a transmission line comprising a pair of electrodes disposed on top of the cladding layer, the electrodes running parallel to the waveguide to both sides of the waveguide;
- and
- one or more nonconductive channels formed underneath the transmission line within at least one of the silicon device layer or the silicon handle and extending to the buried oxide layer, each of the one or more nonconductive channels running parallel to the waveguide and overlapping laterally with a gap between the electrodes but not extending beyond outer edges of the electrodes.
A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
- depositing a dielectric material on top of the silicon device layer to form a cladding layer;
- forming a waveguide within at least one of the silicon device layer or the cladding layer;
- forming, within at least one of the silicon device layer or the silicon handle, one or more nonconductive channels extending to the buried oxide layer and running parallel to the waveguide;
- depositing, patterning, and etching electrode metals on top of the cladding layer to create a pair of electrodes of a transmission line running parallel to the waveguide, wherein the created electrodes are placed such that the one or more nonconductive channels are located in a region underneath the transmission line, overlapping with a gap defined between the electrodes but not extending beyond outer edges of the electrodes.
A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
- depositing a dielectric material on top of the silicon device layer to form a cladding layer;
- forming a waveguide of a first photonic device and a waveguide of a second photonic device within at least one of the silicon device layer or the cladding layer;
- forming, within at least one of the silicon device layer or the silicon handle, confined to a region encompassing only the first photonic device, one or more nonconductive channels extending to the buried oxide layer and running parallel to the waveguide of the first photonic device;
- depositing, patterning, and etching electrode metals on top of the planarized surface to create electrodes of a transmission line of the first photonic device on both sides of the waveguide of the first photonic device, wherein the created electrodes are placed such that the one or more nonconductive channels are located in a region underneath the transmission line, overlapping with a gap defined between the electrodes.
Dependencies are inferred from the claim text.