Sleek serial interface for a wrapper boundary register (device and method)

Device of one of previous claims, further having a counter (211) to control a data transmission size in certain states (READ_DEV_ADR, READ_INSTRUCTION, SEND_IDCODE, READ_DATA and READ_UPDATE) of the state machine (210), the counter receiving the clock signal (SCLK) supplied to the serial interface device.

Device of one of previous claims, the state machine (210) handling transactions between the external master (10) and itself, wherein the state machine (210) is capable to generate an additional Wrapper Boundary Register control signal (WT), e.g. WCH_RESET, to and for the Wrapper Boundary register (WBR,40) of the core device (100).

Device of one of previous claims, wherein the State Machine (210) is configured and capable to generate all Wrapper Boundary Register control signals (30;

• CW, SW, UW, WN) of the given standard, preferably CaptureWR, ShiftWR, UpdateWR and WRSTN of the IEEE 1500 standard, the SelectWIR signal of the IEEE 1500 standard not being a WBR control signal.

Device of one of previous claims, wherein an output signal (WSO) of the Wrapper Boundary Register (40;WBR) is supplied to the serial interface device (201) or directly to the terminal (2b) of the physical Data Output (SDO).

Device of one of previous claims, wherein the logical data input signal (SDI) at physical Data Input Terminal (1a) is supplied, preferably directly, to the WBR (40) as Input Signal (WSI).

Device of one of previous claims, wherein the clock signal (SCLK) from the third terminal (1c) is also supplied, preferably directly, to the WBR (40) as clock signal (WRCK).

Device of one of previous claims, wherein the clock signal (SCLK) from the third terminal (1c) is supplied to the serial interface device (201), preferably therewith to the control logic (209) containing the state machine (210), the Address Register (214) and the Instruction Register (213).

Device of one of previous claims, wherein the logical data input signal (SDI) at physical Data Input Terminal (1a) is supplied to the Address Register (214), the Instruction Register (213) and to the control logic (209) containing the state machine (210), but not to the state machine (210).

Device of one of previous claims, wherein the coupling is an electrical conductive connection.

Device of one of previous claims, further having an Identification Register (215) containing an identification-code (215a) of the core device (100).

Device of one of previous claims, the serial interface device (201) further having an additional device-address source, supplying a device-address (214a) of a corresponding core device (100a) associated with the interface device, when multiple cores (100a, 100b) are on the chip (1) and each core has an own dedicated serial interface device (201a, 201b).

Device of one of previous claims, further having a counter (211), supplied with the clock signal (SCLK) through the third terminal (1c) to control the changes of states (510, 520, 525, 530, 550) of the state machine (210).

Device of one of previous claims, the serial interface device (201) further having an Address Register (214) to receive and hold an address supplied through the physical data input terminal (1a) for comparison with an individual device-address (214a) of this serial interface device (201a) and a corresponding core (100a), when multiple serial interface devices (201a,201b,201c) each attributed to a corresponding core (100a,100b,100c) are present on the chip (1*).

Device of one of previous claims, wherein the control logic (209) has access to an Address Register (214), being configured for holding a received address, the control logic (209) being configured for reading the address as held by the Address Register (214).

Device of one of previous claims, further having a counter (211), supplied with the clock signal (SCLK) through the third terminal (1c) to control at least some changes of states (510, 520, 525, 530, 550) of the state machine (210).

Device of previous claim, wherein at least some changes of states of the state machine (210) depend at least from a counter value of the counter (211) and a wrapper-instruction as read from the Instruction Register (213), the Instruction Register (213) having received the wrapper-instruction through the physical data input terminal (1a).

Device of one of previous claims, further having an Identification Register (215) for holding an ID-Code (215a) identifying the core device (100).

Device of previous claim, the ID-Code of the Identification Register (215) identifying the core device (100) is sent by control of the state machine (210) and a control logic (209) in the serial test interface (201) to the single output terminal (1b) to the external master (10), upon an corresponding wrapper-instruction as read from the Instruction Register (213).

Device of previous claim, the control logic (209) in the serial test interface (201) acts as gateway to the single output terminal (1b) for supplying either—but not both at the same time—the ID-Code (215a) of the Identification Register (215) or the logical output test signal (WSO) returning from the WBR (40) of the core device (100) to the external master (10) by control of the control logic (209) upon an corresponding wrapper-instruction as read from the Instruction Register (213).

Device of one of previous claims, further having a power-on detector (20) for supplying a power on reset signal to the serial test interface (201) and the Wrapper Boundary Register (40) of the core (100) for common initialisation.

Device of one of previous claims, the clock signal (SCLK) supplied through the third terminal (1c) is supplied to the WBR (40) and the serial test interface (201).

Test method of testing wrapped cores (100a, 100b, 100c) within a System-on-Chip (SoC;1*), wherein

• each core of the wrapped cores (100a, 100b, 100c) having an associated serial interface device (201a, 201b, 201c);
• each interface device having a unique device address (214a, 214b, 214c), not being the same, although a structure of all serial interface devices (201a, 201b, 201c) is the same.

-44. (canceled)

Method to generate additional Wrapper Boundary Register (WBR) control signals (30) by a state machine (210) on a chip (1,1*), the method comprising the steps of

• generation of at least one additional WBR control signal by the state machine (210) upon completion of a READ_INSTRUCTION state, in an IDLE state, whenever the Instruction Register (213) contains an additionally defined wrapper instruction with a non-data-transfer function;
• defining one additional signal (WCH RESET), and thereby the additional signal sets back or resets one or more access signals in the Wrapper Boundary Register (40).

Layout for a serial test interface comprising a layout for an Instruction Register (213) to receive and hold wrapper-instructions supplied through a representation of a physical data input terminal (2a) and a layout of a state machine (210) for handling transactions supplied thereto, wherein the state machine is layouted to read a wrapper-instruction from the Instruction Register (213) and generate and provide wrapper control signals (30) of the given standard for a core device (100) having the Wrapper Boundary Register (40) according to the wrapper-instruction read from the Instruction Register;

• and the representation of the single input terminal (2a) is provided to supply an input test signal (SDI) coupled to the Wrapper Boundary Register (40) as logical input test signal (WSI);
• a representation of a single output terminal (2b) is provided to return an output test signal (SDO) coupled (209) to the representation of the output terminal (2b) from an output (WSO) of the Wrapper Boundary Register (40) of the core device (100).