Jtag support over a broadcast bus in a distributed memory buffer system

An apparatus for testing a plurality of semiconductor chips in a distributed memory buffer system, the apparatus comprising;

• an Address and Command (AC) chip;
• a Joint Test Action Group (JTAG) Test Access Port (TAP) controller disposed in the AC chip;
• a JTAG internal test converter disposed in the AC chip;
• a mainline logic disposed in the AC chip;
• a JTAG test port connected to the AC chip;
• a shared broadcast bus connected to the AC chip;
• a return open drain line connected to the AC chip;
• and
• one or more data chips connected to the shared broadcast bus and the return open drain line.

A system for testing a plurality of semiconductor chips in a distributed memory buffer system, the system comprising;

• an Address and Command (AC) chip;
• a Joint Test Action Group (JTAG) Test Access Port (TAP) controller disposed in the AC chip;
• a JTAG internal test converter disposed in the AC chip;
• a mainline logic disposed in the AC chip;
• a JTAG test port connected to the AC chip;
• a shared broadcast bus connected to the AC chip;
• a return open drain line connected to the AC chip;
• one or more data chips connected to the shared broadcast bus and the return open drain line;
• a JTAG Automated Test Equipment (ATE) connected to the JTAG test port;
• and
• a test server connected to the JTAG automatic test equipment over a network.