Synchronized pulsed lada for the simultaneous acquisition of timing diagrams and laser-induced upsets

A method using laser assisted device alteration (LADA) for testing an integrated device under test (DUT) that is coupled to a testing equipment (TE) the TE generating a clock signal and a test signal, the method comprising:

• generating a laser beam comprising a train of laser pulses;
• sequentially positioning the laser beam on each pixel location within an area of interest of the DUT and performing a test loop at each pixel location, wherein the test loop comprises temporally scanning arrival time of the laser pulses with respect to the clock signal while the ATE applies the test signal to the DUT and for each spatiotemporal volume recording a pass/fail result of the DUT, wherein spatiotemporal volume is defined as a combination of a spatial coordinate on the DUT and arrival time of a laser pulse;
• and,
• generating a plot of failure rate versus time for a plurality of pixel locations for which pass/fail results indicate a failure rate deviating from a predetermined value.

A method using laser assisted device alteration (LADA) for testing an integrated device under test (DUT) that is coupled to a testing equipment (TE) the TE generating a clock signal and a test signal, the method comprising:

• configuring the TE to apply to the DUT test pattern causing transistors in the DUT to fail at least one of the tests without the application of laser pulses;
• applying the test pattern repetitively to the DUT while applying laser pulses at selected focus locations of the DUT, the laser pulses being configured to have sufficient energy to inject charge carrier pair at precise times during the test pattern;
• recording the tester results for each test pattern repetition at each focus location;
• determining locations where test results substantially diverge from 50% failure;
• generating a sequence of failure rate versus time progression at locations wherein the failure rate substantially diverges.