Mask Optimization Process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDaniel Beylkin, Sagar Vinodbhai Trivedi
Life of this patent
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Abstract
A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.
Claims20
A method performed by a computing system, the method comprising:
- receiving a layout pattern;
- receiving a target pattern associated with the layout pattern;
- receiving a set of constraints related to the target pattern;
- simulating a first contour associated with the layout pattern;
- determining a first difference between the first contour and the target pattern;
- simulating a second contour associated with a modified layout pattern;
- determining a second difference between the second contour and a modified target pattern, the modified target pattern being different than the target pattern and within the constraints;
- and
- fabricating a mask having the final layout pattern.
A method performed by a computing system, the method comprising:
- receiving a layout pattern;
- receiving a target pattern associated with the layout pattern;
- receiving a set of constraints related to the target pattern;
- iteratively simulating contours of layout pattern variations across a target pattern space, the target pattern space comprising a variation of the target pattern within the constraints;
- selecting a final layout pattern and a final target pattern from the target pattern space;
- and
- fabricating a mask having the final layout pattern.
A system comprising:
- a processor;
- and
- a memory comprising machine readable instructions that when executed by the processor cause the system to:
- receive a layout pattern and a target pattern associated with the layout pattern;
- receive a set of constraints related to the target pattern, the constraints placing limits on target pattern variation;
- iteratively simulate contours of layout pattern variations across a target pattern space within the constraints;
- and
- select a final layout pattern and a final target pattern from the target pattern space, wherein a simulated contour of the final layout pattern has a minimal difference from the final target pattern across the target pattern space.
Dependencies are inferred from the claim text.