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AssigneeInternational Business Machines Corporation
InventorsWooram Lee, Bodhisatwa Sadhu, Alberto Valdes Garcia
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A method and system of providing harmonic frequency multiplication are provided. An input signal having a frequency f, is received by a programmable timing circuit. A signal that is in phase with the input signal, is provided at the first output of the programmable timing circuit. A time delayed version of the input signal, having the frequency f, is provided at the second output of the programmable timing circuit. A signal having the frequency f, is provided at the output of a first buffer. A duty cycled controlled signal having the frequency f, is provided at the output of the second buffer. A frequency nf, where n is a positive integer, is provided at the output of the multiplier. A higher-order frequency multiplied signal based on the frequencies f and nf, is provided at the output of a mixer.
A harmonic frequency multiplier device, comprising:
A method of providing harmonic frequency multiplication using programmable timing circuit, a first buffer coupled to a first output of the programmable timing circuit, a second buffer coupled to a second output of the programmable timing circuit, a frequency multiplier coupled to an output of the second buffer, and a mixer coupled to an output of the first buffer and an output of the multiplier, the comprising:
Dependencies are inferred from the claim text.