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US 2019/0156908 A1Published application
Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths
AssigneeTexas Instruments Incorporated
InventorsDevanathan Varadarajan, Lei Wu
Life of this patent
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Abstract
A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.
Claims21
A device comprising:
- one or more cores under test;
- a clock control circuit coupled to the cores under test, that selectively provides a slow-speed operation or an at-speed operation for an enabled clock;
- and
- a built-in-self-test (BIST) controller coupled to the cores under test;
- wherein each core under test includes:
- one or more memories;
- a clock gating circuit that selectively enables clocks to drive test sequences to inputs of the memories or to capture the output of the memories;
- a mode control circuit that selectively controls a test mode on the inputs of the memories or the outputs of the memories, wherein selective control of the test mode is implemented during the slow-speed operation or the at-speed operation of the enabled clock.
5 more elements
A method of testing a functional memory interface logic at-speed, the method comprising:
- generating test sequences for memory of a core under test by a built-in-self-test (BIST) controller;
- selectively enable clocks to drive the test sequences to an input of the memory or to capture the output of the memory;
- selecting a slow-speed or at-speed operation for an enabled clock;
- selecting a test mode on the input of the memory or the output of the memory, wherein the selective control of the test mode is implemented during the selected slow-speed or at-speed operation of the enabled clock.
1 more element
A method comprising:
- generating test sequences for memory of a core under test by a built-in-self-test (BIST) controller;
- selectively enabling clocks to drive the test sequences to a memory input or to capture the output of the memory of the core under tests;
- selectively providing a slow-speed or at-speed operation for an enabled clock;
- selectively controlling a BIST mode or a functional mode on the input of the memory or output of the memory, wherein the BIST mode is implemented using the slow-speed operation while the functional mode utilizes the at-speed operation for the enabled clock.
1 more element
Dependencies are inferred from the claim text.