Simultaneous scan chain initialization with disparate latches

A design structure tangibly embodied in a machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a reset electrically connected to a reset input of a first latch, a select line of a multiplexor an OR gate, the multiplexor receives data from a power source, both the multiplexor and the OR gate comprise a circuit, the first latch comprising the reset input, a data port, a scan enable input, a clock input, and a data output;
• a first regular logic data path electrically connected to the first latch data port;
• the first latch data output electrically connected to a second regular logic data path;
• the second regular logic data path electrically connected to the multiplexor;
• a first clock electrically connected to the first latch clock input;
• a second clock electrically connected to the OR gate;
• the OR gate electrically connected to a clock input of a second latch, the second latch includes the clock input, a scan enable input, a data input, and a data output;
• the multiplexor electrically connected to the data port of the latch;
• and
• the second latch data output electrically connected to a third regular logic data path.

An integrated circuit comprising:

• a reset electrically connected to a select line of a multiplexor and an OR gate, wherein both the multiplexor and the OR gate comprise a circuit, wherein the multiplexor receives data from a power source;
• a clock electrically connected to the OR gate,
• wherein the OR gate is electrically connected to a clock input of a first latch, wherein the first latch includes the clock input, a scan enable input, a data input, and a data output;
• and
• a first regular logic data path electrically connected to the multiplexor, wherein the multiplexor is further electrically connected to the data port of the first latch.