Sensing in floating source string nor architecture
AssigneeSunrise Memory Corporation
InventorRaul Adrian Cernea
Life of this patent
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Abstract
Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.
Claims45
A method of retrieving information stored in a memory cell among a plurality of memory cells which share a common bit line, each memory cell being associated with a common source line and with a word line, the method comprising:
- initializing the common bit line and the associated common source line to a predetermined voltage between a power supply voltage and ground;
- effectuating a voltage separation between the associated common source line and the common bit line by causing the common bit line, the associated common source line, or both, to deviate from the predetermined voltage;
- on the associated word line, providing a read voltage to place the memory cell in a conductive state that corresponds to the information stored in the memory cell;
- and
- using a sense circuit, determining the conductive state based on sensing a flow of charge into or out of the associated common source line as a result of the read voltage on the associated word line.
A method of retrieving information stored in an addressed memory cell among a plurality of memory cells which share a common source line and a common bit line, the common bit line connecting selectably to an input terminal of a sensing circuit by a selection device or circuit, and wherein each memory cell is associated with a word line among a plurality of word lines, the method comprising:
- initializing both the common bit line and the common source line to a first voltage between a power supply voltage and ground by temporarily connecting the bit line to the input terminal of the sensing circuit and temporarily connecting the common bit line and the common source line by rendering conducting one or more designated transistors;
- disconnecting the common bit line from the common source line by rendering the designated transistors non-conducting, thereby floating the common source line about the first voltage;
- using the selection device or circuit, creating a voltage difference between the common bit line and the common source line by imposing a second voltage on the common bit line and a third voltage at the input terminal of the sensing circuit, the third voltage being different from the second voltage;
- providing a read voltage on the word line associated with the addressed memory cell to place the addressed memory cell in a conductive state corresponding to the information stored in the addressed memory cell, thereby enabling a flow of charge between the capacitances in the common source line and the common bit line;
- and
- determining the conductive state of the addressed memory cell based on detecting the flow of charge.
Dependencies are inferred from the claim text.