Non-volatile memory device and method of erasing the same

A non-volatile memory device comprising:

• a substrate;
• a memory cell array comprising a plurality of gate conductive layers stacked on the substrate and a plurality of pillars penetrating through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the substrate, wherein at least one of the plurality of gate conductive layers is a ground select line;
• a control logic circuit configured to output an erase enable signal for controlling an erase operation with respect to the memory cell array;
• a substrate bias circuit configured to, in response to the erase enable signal, output a first target voltage to the substrate as a substrate bias voltage during a first delay time and, after the first delay time, output the substrate bias voltage to the substrate while gradually increasing a level of the substrate bias voltage to that of an erase voltage having a higher level than the first target voltage;
• and
• a row decoder configured to apply a ground voltage to the ground select line based on control of the control logic circuit during the first delay time.