US 2019/0156883 A1 · NEUROMORPHIC COMPUTING DEVICE

Abstract

A neuromorphic computing device includes a plurality of row lines, a plurality of column lines and a plurality of synapses. The synapses are positioned at intersections of the row lines and column lines, respectively. The synapses include a first synapse and a second synapse. The first synapse includes a first resistance-adjustable element and a first transistor connected to the first resistance-adjustable element in series. The first transistor has a first aspect ratio and is configured to receive a first turn-on voltage. The second synapse includes a second resistance-adjustable element and a second transistor connected to the second resistance-adjustable element in series. The second transistor has a second aspect ratio and is configured to receive a second turn-on voltage. The first aspect ratio differs from the second aspect ratio, and/or the first turn-on voltage differs from the second turn-on voltage.

Claims20

Dependent claims

A neuromorphic computing device comprising:

a plurality of row lines;
a plurality of column lines;
and
a plurality of synapses, positioned at intersections of the row lines and column lines, respectively, the synapses comprising:
a first synapse comprising:
a first resistance-adjustable element configured to be binarily set at a low resistance state or a high resistance state to function as a first switch element;
and
a first transistor, connected to the first resistance-adjustable element in series, the first transistor having a first aspect ratio and being configured to receive a first turn-on voltage;
and
a second synapse comprising:
a second resistance-adjustable element configured to be binarily set at a low resistance state or a high resistance state to function as a second switch element;
and
a second transistor, connected to the second resistance-adjustable element in series, the second transistor having a second aspect ratio and being configured to receive a second turn-on voltage;
wherein the first aspect ratio differs from the second aspect ratio, and/or the first turn-on voltage differs from the second turn-on voltage.

11 more elements

A neuromorphic computing device, adapted to perform a sum-of-product calculation on an input vector, the neuromorphic computing device comprising:

a plurality of row lines configured to receive the input vector;
a plurality of column lines configured to output a result of sum-of-product of the input vector and a weighting vector;
and
a plurality of synapses positioned at intersections of the row lines and column lines, respectively, and configured to form the weighting vector, the synapses comprising:
a first synapse comprising:
a first resistance-adjustable element, configured to be binarily set at a low resistance state or a high resistance state to function as a first switch element;
and
a first transistor, connected to the first resistance-adjustable element in series, wherein when the first resistance-adjustable element is set at the low resistance state, a first conductivity of the first transistor represents a first weighting value of the first synapse, the first weighting value is included in the weighting vector;
and
a second synapse comprising:
a second resistance-adjustable element, configured to be binarily set at the low resistance state or the high resistance state to function as a second switch element;
and
a second transistor, connected to the second resistance-adjustable element in series, wherein when the second resistance-adjustable element is set at the low resistance state, a second conductivity of the second transistor represents a second weighting value of the second synapse, and the second weighting value is included in the weighting vector.

10 more elements

Dependencies are inferred from the claim text.

Neuromorphic computing device

Life of this patent

Neuromorphic computing device

Life of this patent

Abstract

Claims20