High speed fpga boot-up through concurrent multi-frame configuration scheme

A programmable integrated circuit device, comprising:

• a first data line segment of a plurality of data line segments, wherein the first data line segment comprises:
• a first plurality of configuration random access memory (CRAM) cells;
• and
• a first pipeline column coupled to the first plurality of CRAMs, wherein the first pipeline column is configured to:
• receive a plurality of data frames;
• transmit a first data frame of the plurality of data frames to the first plurality of CRAMs, wherein the first data frame is associated with the first data line segment;
• and
• transmit a second data frame of the plurality of data frames to a second data line segment of the plurality of data line segments, wherein the second data frame is associated with the second data line segment, and wherein the second data line segment comprises a second pipeline column coupled to a second plurality of CRAMs.

A method for operating a programmable integrated circuit device, comprising:

• receiving, via a pipeline column of a data line segment, a plurality of data frames;
• transmitting, via the pipeline column, a first data frame of the plurality of data frames to a plurality of configuration random access memory (CRAM) cells of the data line segment, wherein the first data frame is associated with the data line segment;
• and
• transmitting, via the pipeline column, a second data frame of the plurality of data frames to an additional plurality of CRAMs of an additional data line segments, wherein the second data frame is associated with the additional data line segment.

A non-transitory machine-readable medium comprising instructions stored thereon for configuring a programmable integrated circuit device, the instructions comprising:

• instructions to receive a plurality of data frames at a pipeline column of a data line segment;
• instructions to transmit, via the pipeline column, a first data frame of the plurality of data frames to a plurality of memory cells of the data line segment, wherein the first data frame is associated with the data line segment;
• and
• instructions to transmit, via the pipeline column, a second data frame of the plurality of data frames to an additional pipeline column of an additional data line segment.