Display device including timing controller

A display device, comprising:

• pixels arranged in rows and columns;
• gate drivers connected to the rows of the pixels through gate lines;
• source drivers connected to the columns of the pixels through source lines;
• and
• a timing controller configured to control the gate drivers and the source drivers,
• wherein the timing controller comprises:
• an address generator configured to receive a previous value and a current value of a specific pixel and generate an address based on the previous value and the current value;
• a cache memory configured to receive the address, output one of first candidate overdrive values and second candidate overdrive values in response to one of the first candidate overdrive values and the second candidate overdrive values corresponding to the address being stored, and output the address in response to one of the first candidate overdrive values and the second candidate overdrive values being not stored;
• a memory configured to store look-up tables (LUTs) and transmit one of the first candidate overdrive values and the second candidate overdrive values associated with the address from the LUTs to the cache memory in response to the address being received from the cache memory;
• a first interpolator configured to output a first overdrive value by interpolating the first candidate overdrive values and output a second overdrive value by interpolating the second candidate overdrive values;
• and
• a second interpolator configured to output a final overdrive value by interpolating the first overdrive value and the second overdrive value, and
• wherein each of the source drivers supplies an overdrive voltage corresponding to the final overdrive value to a source line connected to the specific pixel and supplies a source line voltage corresponding to the current value of the specific pixel to the source line.

A display device, comprising:

• pixels arranged in rows and columns;
• gate drivers connected to the rows of the pixels through gate lines;
• source drivers connected to the columns of the pixels through source lines;
• and
• a timing controller configured to control the gate drivers and the source drivers,
• wherein the timing controller comprises an overdrive controller configured to:
• store look-up tables (LUTs) including candidate overdrive values according to previous values and current values with respect to reference pixels among the pixels;
• generate overdrive values associated with a previous value and a current value of a specific pixel from specific LUTs associated with the specific pixel of a selected row among the pixels among the LUTs;
• and
• output a final overdrive value of the specific pixel by interpolating the overdrive values,
• wherein a source driver associated with the specific pixel among the source drivers supplies an overdrive voltage corresponding to the final overdrive value to a source line connected to the specific pixel and supplies a source line voltage corresponding to the current value of the specific pixel to the source line, and
• wherein the overdrive controller is further configured to select the current value as the final overdrive value in response to a difference between the previous value and the current value of the specific pixel being less than a threshold value.