Structure design generation for fixing metal tip-to-tip across cell boundary
AssigneeInternational Business Machines Corporation
InventorsGeng Han, Dongbing Shao
Life of this patent
Estimating the term…
Abstract
A method for semiconductor structure design includes performing, by a processor, error processing of an initial design file layout. The processor further detects a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules. Upon detection of the T2T structure design violation, the processor retargets the Vx for generating a resulting design file layout of the semiconductor structure.
Claims20
A method for semiconductor structure design comprising:
- performing, by a processor, error processing of an initial design file layout;
- detecting, by the processor, a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules;
- and
- upon detection of the T2T structure design violation, retargeting, by the processor, the Vx for generating a resulting design file layout of the semiconductor structure.
A computer program product for generating a semiconductor structure design, the computer program product comprising a computer readable storage device having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:
- performing, by the computer, error processing of an initial design file layout;
- detect, by the computer, a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for a semiconductor structure based on a library of pattern rules;
- and
- upon detection of the T2T structure design violation, retarget the Vx for generating a resulting design file layout of the semiconductor structure.
A method for generating a semiconductor structure design comprising:
- performing, by a processor, error processing of an initial design file layout using a library of pattern rules;
- detecting, by the processor, a tip-to-tip (T2T) structure design violation at a design cell boundary for a metal layer above (Ma) a via (Vx) at a tip of the Ma for the initial design file layout for the semiconductor structure based on pattern checking using the library of pattern rules;
- and
- upon detection of the T2T structure design violation, retargeting using the retargeting tables, by the processor, design values for the Vx for generating a resulting design file layout of the semiconductor structure.
Dependencies are inferred from the claim text.