Secure environment in a non-secure microcontroller

An Internet of Things (IoT) device, comprising:

• a microcontroller having a microprocessor and a memory configured internal to the microcontroller, the internal memory having a secure environment configured therein, the secure environment having secure environment configuration instructions executable by the microprocessor and secure engine program instructions executable by the microprocessor, wherein after recognizing a boot-sequence, the microprocessor directed to:
• via the secure environment configuration instructions:
• disable each direct memory access (DMA)controller that is configurable to access memory of the secure environment;
• configure at least one memory controller for access to the secure environment;
• prevent the microprocessor from executing instructions fetched from outside the secure environment;
• via the secure engine program instructions:
• only permit execution of instructions fetched from the secure environment;
• disable interrupts;
• perform at least one secure operation after interrupts are disabled;
• and
• enable interrupts after performing the at least one secure operations;
• and
• via the secure environment configuration instructions:
• clear memory;
• and
• restore an enable/disable status of each DMA controller disabled after recognizing the boot-sequence.

A non-transitory computer-readable storage medium whose stored contents configure a computing system to implement a secure engine method, the secure engine method comprising:

• restricting user-level access to a secure environment defined in the non-transitory computer-readable storage medium;
• detecting a boot-sequence, and after detecting the boot-sequence:
• disabling direct memory access (DMA) controllers;
• configuring at least one memory controller for access to the secure environment by a secure engine;
• preventing execution of any instructions fetched from outside the secure environment;
• executing secure engine program instructions, said executing including:
• disabling interrupts;
• performing at least one secure operation after interrupts are disabled;
• and
• enabling interrupts after performing the at least one secure operation;
• clearing at least some volatile memory;
• re-enabling the disabled DMA controllers;
• and
• performing user-level operations.