Digital correlated double sampling circuits and image sensors including the same

A digital correlated double sampling (CDS) circuit comprising:

• a first latch circuit configured to latch an input phase shift code based on a first control signal to sequentially store a first phase shift code and a second phase shift code, the first phase shift code representing a reset component, the second phase shift code representing an image component;
• a first converting circuit configured to convert the first phase shift code and the second phase shift code into a first Gray code and a second Gray code, respectively;
• a second latch circuit configured to latch an output of the first converting circuit based on a second control signal to store the first Gray code;
• a second converting circuit configured to convert the first Gray code and the second Gray code into a first binary code and a second binary code, respectively;
• and
• a calculating circuit configured to subtract the reset component from the image component based on the first binary code and the second binary code to generate a third binary code, and to sequentially output the third binary code, the third binary code representing an effective image component.

An image sensor comprising:

• a pixel array configured to generate a plurality of analog pixel signals based on incident light;
• a comparison block configured to compare the plurality of analog pixel signals with a ramp signal to generate a plurality of first control signals and a plurality of second control signals;
• and
• a digital correlated double sampling (CDS) block including a plurality of digital CDS circuits, the digital CDS block configured to perform a digital CDS based on the plurality of first control signals, the plurality of second control signals, and an input phase shift code to generate a plurality of effective image binary codes,
• wherein each of the plurality of digital CDS circuits comprises:
• a first latch circuit configured to latch the input phase shift code based on one of the plurality of first control signals to sequentially store a first phase shift code and a second phase shift code, the first phase shift code representing a reset component, the second phase shift code representing an image component;
• a first converting circuit configured to convert the first phase shift code and the second phase shift code into a first Gray code and a second Gray code, respectively;
• a second converting circuit configured to convert the first Gray code and the second Gray code into a first binary code and a second binary code, respectively;
• a second latch circuit configured to store the first binary code or the first Gray code based on one of the plurality of second control signals;
• and
• a calculating circuit configured to subtract the reset component from the image component based on the first binary code and the second binary code to generate a third binary code, and to sequentially output the third binary code, the third binary code representing an effective image component.