Electronic Systems and Methods of Forming Semiconductor Constructions
AssigneeMicron Technology, Inc.
InventorsZailong Bian, Janos Fucsko
Life of this patent
Estimating the term…
Abstract
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
Claims30
1-19. (canceled)
An electronic system, comprising:
- a processor;
- a memory device in data communication with the processor;
- and
- wherein at least one of the memory device and the processor includes one or more electrical isolation regions contained within electrically insulative liners and comprising lower narrow portions joining to upper wide portions at steps;
- the one or more electrical isolation regions comprising a non-gaseous material within the narrow portions and wide portions, and comprising voids substantially entirely contained within the narrow portions.
(canceled)
A method of forming a semiconductor construction, comprising:
- providing a semiconductor substrate;
- forming a trench in the substrate, the trench having a lower region and an upper region over the lower region;
- forming a liner within the trench to narrow the trench;
- providing a sacrificial material which is along the liner within the lower region of the trench and not along the liner within the upper region of the trench;
- while the sacrificial material is along the liner within the lower region of the trench, reducing the thickness of the liner along the upper region of the trench;
- removing the sacrificial material;
- and
- forming electrically insulative material within the trench and along the liner, the electrically insulative material substantially filling the upper region of the trench and leaving a void within the lower region of the trench.
(canceled)
(canceled)
32-33. (canceled)
(canceled)
A method of forming a semiconductor construction, comprising:
- providing a semiconductor substrate;
- forming a trench in the substrate;
- partially filling the trench with a first material to narrow the trench, the first material having a first thickness;
- reducing the thickness of the first material along an upper region of the trench while the thickness of the first material along a lower region of the trench remains at the first thickness;
- after said reducing of the thickness, the narrowed trench having a wide upper portion joining a constricted lower portion at a step;
- and
- forming electrically insulative second material within the narrowed trench, the electrically insulative second material substantially filling the wide upper portion and leaving a void within the constricted lower portion.
(canceled)
A method of forming a semiconductor construction, comprising:
- providing a semiconductor substrate;
- forming a trench in the substrate, the trench having a lower region and an upper region over the lower region;
- forming a liner within the trench to narrow the trench;
- providing non-oxidized silicon to be along the liner within the lower region of the trench and not along the liner within the upper region of the trench;
- while the non-oxidized silicon is along the liner within the lower region of the trench, reducing the thickness of the liner along the upper region of the trench;
- converting the non-oxidized silicon to silicon dioxide;
- and
- after reducing the thickness of the liner along the upper region of the trench, forming electrically insulative material over the silicon dioxide to fill the upper region of the trench.
44-45. (canceled)
(canceled)
Dependencies are inferred from the claim text.