US 2019/0096799 A1 · TAPERING DISCRETE INTERCONNECTION FOR AN INTEGRATED CIRCUIT (IC)

Abstract

A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is configured and arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.

Claims20

Dependent claims

An integrated circuit, comprising:

a first electronic circuit;
a second electronic circuit;
a discrete tapering interconnection coupled between the first electronic circuit and the second electronic circuit, the discrete tapering interconnection including:
a first set of parallel conductors from among a plurality of conductors situated in a first metal layer of a plurality of metal layers of a semiconductor stack, the first set of parallel conductors being configured and arranged to form a discrete tapering of the first set of parallel conductors between the first electronic circuit and the second electronic circuit, and
a second set of parallel conductors from among the plurality of conductors, situated in a second metal layer of the plurality of metal layers of the semiconductor stack, the second set of parallel conductors being configured and arranged to provide a plurality of interconnections among the first set, of parallel conductors.

2 more elements

An asymmetric discrete tapering interconnection, comprising:

a first set of parallel conductors from among a plurality of conductors situated in a first metal layer of a plurality of metal layers of a semiconductor stack, each conductor from among the first set of parallel conductors being characterized as having a length from among a plurality of lengths, the plurality of lengths being different from one another to form an asymmetric discrete tapering of the first set of parallel conductors;
and
a second set of parallel conductors from among the plurality of conductors, situated in a second metal layer of the plurality of metal layers of the semiconductor stack, the second set of parallel conductors being configured and arranged to provide a plurality of interconnections among the first set of parallel conductors.

A symmetric discrete tapering interconnection, comprising:

a first set of parallel conductors from among a plurality of conductors situated in a first metal layer of a plurality of metal layers of a semiconductor stack,
wherein the first set of parallel conductors is characterized as including a plurality of groups of conductors, each group of conductors from among the plurality of groups of conductors including at least two conductors from among the first set of parallel conductors, and
wherein each group of conductors from among the plurality of groups of conductors is characterized as having a length from among a plurality of lengths, the plurality of lengths being different from one another to form a symmetric discrete tapering of the first set of parallel conductors;
and
a second set of parallel conductors from among the plurality of conductors, situated in a second metal layer of the plurality of metal layers of the semiconductor stack, the second set of parallel conductors being configured and arranged to provide a plurality of interconnections among the first set of parallel conductors.

2 more elements

Dependencies are inferred from the claim text.

Tapering discrete interconnection for an integrated circuit (ic)

Life of this patent

Tapering discrete interconnection for an integrated circuit (ic)

Life of this patent

Abstract

Claims20