Semiconductor devices

A semiconductor device comprising:

• a substrate comprising a cell array region including a buried gate structure, and a peripheral region including a NMOS region and a PMOS region having different conductivity types;
• a first transistor in the NMOS region, wherein the first transistor includes a first gate stack, a first source/drain region on at least one side of the first gate stack, and a first channel region below the first gate stack;
• and
• a second transistor in the PMOS region, wherein the first transistor includes a second gate stack, a second source/drain region on at least one side of the second gate stack, and a second channel region below the second gate stack,
• wherein the first gate stack includes a first high-dielectric constant insulating film, a first gate electrode layer having a first thickness, a second gate electrode layer, a third gate electrode layer, and a first silicon layer which are sequentially laminated,
• wherein the second gate stack includes a second high-dielectric constant insulating film, a fourth gate electrode layer having a second thickness greater than the first thickness, a fifth gate electrode layer, a sixth gate electrode layer, and a second silicon layer which are sequentially laminated,
• wherein the first channel region and the second channel region include materials different from each other, and
• wherein the second gate electrode layer and the fifth gate electrode layer includes lanthanum.

A semiconductor device comprising:

• a substrate including an NMOS region and a PMOS region;
• a first gate stack on the substrate in the NMOS region;
• a first channel region below the first gate stack;
• a second gate stack on the substrate in the PMOS region;
• and
• a second channel region which is below the second gate stack and includes a material different from the first channel region,
• wherein the first gate stack includes a first high-dielectric constant insulating film, a first gate electrode layer, a second gate electrode layer, a third gate electrode layer, and a first silicon layer which are sequentially laminated,
• wherein the second gate stack includes a second high-dielectric constant insulating film, a fourth gate electrode layer, a fifth gate electrode layer, a sixth gate electrode layer, and a second silicon layer which are sequentially laminated,
• wherein the second channel region includes germanium,
• wherein the first gate electrode layer and the fourth gate electrode layer include the same metal element,
• wherein the second gate electrode layer includes lanthanum, and
• wherein the fifth gate electrode layer includes lanthanum or aluminum.