Fin isolation structures of semiconductor devices

A semiconductor structure, comprising:

• a substrate;
• a shallow trench isolation (STI) region on the substrate;
• a first fin on the substrate, wherein an upper portion of the first fin protrudes from a top surface of the STI region and comprises a first vertical dimension;
• a second fin on the substrate and adjacent to the first fin, wherein:
• an upper portion of the second fin protrudes from the top surface of the STI region;
• the upper portion of the second fin comprises a second vertical dimension less than the first vertical dimension;
• and
• the upper portion of the second fin comprises a horizontal dimension that varies along a vertical direction;
• and
• a gate structure formed on the upper portions of the first and second fins.

A fin field effect transistor (finFET) on a substrate, the finFET comprising:

• a fin structure on the substrate, the fin structure having first and second fin portions adjacent to each other, the first fin portion having a material that is different from an oxide material of the second fin portion;
• an epitaxial region on the first fin portion;
• an etch stop layer on the epitaxial region and on the second fin portion;
• first and second gate structures on the first and second fin portions, respectively;
• and
• a source/drain contact structure on the epitaxial region.