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US 2019/0096764 A1Published application
Semi-sequential 3D Integration
AssigneeImec Vzw
InventorsAmey Mahadev Walke, Nadine Collaert
Life of this patent
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Abstract
Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.
Claims8
A structure comprising:
- a host substrate;
- one or more bonding layers on top of the host substrate;
- and
- an entity on the one or more bonding layers, wherein the entity comprises a first and a second transistor on opposite sides of a common layer of channel material, wherein the first and second transistors each comprise a respective gate, wherein the respective gates overlap each other, wherein the first and second transistors share the same source and drain regions, and wherein the first and second transistors each have a respective channel defined within a same portion of the common layer of channel material overlapped by the respective gates of the first and second transistors.
1 more element
Dependencies are inferred from the claim text.