Cross point memory control
AssigneeIntel Corporation
InventorsRaymond W. ZENG, Mase J. TAUB, Kiran PANGAL, Sandeep K. GULIANI
Life of this patent
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Abstract
The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
Claims41
(canceled)
An apparatus comprising:
- an interface to connect with one or more memory devices based at least, in part, on connection of the one or more memory devices with the interface and
- a controller communicatively coupled to the interface, the controller to:
- receive a request to access one or more memory cells of at least one of the one or more memory devices;
- determine a region location associated with the one or more memory cells;
- and
- provide at least one control parameter for at least one control signal based, at least in part, on the region location, wherein:
- the at least one control parameter comprises a signal amplitude value and a signal time duration and
- the at least one control signal comprises one or more of:
- a set signal and a reset signal.
A method comprising:
- receiving a request to access one or more memory cells of at least one memory device;
- determining a region location associated with the one or more memory cells;
- and
- providing at least one control parameter for at least one control signal based, at least in part, on the region location, wherein:
- the at least one control parameter comprises a signal amplitude value and a signal time duration and
- the at least one control signal comprises one or more of:
- a set signal and a reset signal.
At least one computer-readable medium, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
- receive a request to access one or more memory cells of at least one of the one or more memory devices;
- determine a region location associated with the one or more memory cells;
- and
- provide at least one control parameter for at least one control signal based, at least in part, on the region location, wherein:
- the at least one control parameter comprises a signal amplitude value and a signal time duration and
- the at least one control signal comprises one or more of:
- a set signal and a reset signal.
A system comprising:
- one or more processors;
- one or more memory devices;
- and
- a controller communicatively coupled to the one or more processors and the one or more memory devices, the controller to:
- receive a request to access one or more memory cells of at least one of the one or more memory devices;
- determine a region location associated with the one or more memory cells;
- and
- provide at least one control parameter for at least one control signal based, at least in part, on the region location, wherein:
- the at least one control parameter comprises a signal amplitude value and a signal time duration and
- the at least one control signal comprises one or more of:
- a set signal and a reset signal.
Dependencies are inferred from the claim text.