Phase-change memory with selectors in bjt technology and differential-reading method thereof

A method for reading logic data stored in a phase-change memory device comprising:

• a memory array including:
• a first local bitline connected to a first memory cell that comprises a first selector in BJT technology arranged in series with a first phase-change element having a first value of resistance associated with a first logic datum, wherein the first local bitline has a first parasitic capacitance;
• a second local bitline connected to a second memory cell that comprises a second selector in BJT technology arranged in series with a second phase-change element having a second value of resistance, different from the first value of resistance, second value of resistance associated with a second logic datum, wherein the second local bitline has a second parasitic capacitance;
• a first main bitline having a third parasitic capacitance;
• and
• a second main bitline, having a fourth parasitic capacitance;
• a supply line, designed to supply a first supply voltage;
• a first precharging switch between the first main bitline and the supply line;
• a second precharging switch between the second main bitline and the supply line;
• a first local switch between the first local bitline and the first main bitline;
• a second local switch between the second local bitline and the second main bitline;
• the method comprising:
• at a first instant, closing the first and second precharging switches in order to charge the third and fourth parasitic capacitances at the first supply voltage;
• at a second instant temporally subsequent to the first instant, opening the first and second precharging switches and closing the first and second local switches in order to charge the first and second parasitic capacitances using the voltage of the third and fourth parasitic capacitances;
• at a third instant temporally subsequent to the second instant, activating the first selector in order to enable a discharge of the first and third parasitic capacitances through the first memory cell at a first discharge rate that is a function of the first value of resistance, and activating the second selector to enable a discharge of the second and fourth parasitic capacitances through the second memory cell at a second discharge rate that is a function of the second value of resistance;
• and
• comparing with one another the first and second discharge rates and generating a result of the comparison, thus reading the logic datum.

A phase-change memory device, comprising:

• a memory array including:
• a first local bitline connected to a first memory cell that comprises a first selector in BJT technology arranged in series with a first phase-change element, wherein the first local bitline has a first parasitic capacitance;
• a second local bitline connected to a second memory cell that comprises a second selector in BJT technology arranged in series with a second phase-change element, wherein the second local bitline has a second parasitic capacitance;
• a first main bitline having a third parasitic capacitance, wherein both the first parasitic capacitance and the third parasitic capacitance are coupled to a ground terminal and to a first intermediate node;
• and
• a second main bitline, having a fourth parasitic capacitance, wherein both the second parasitic capacitance and the fourth parasitic capacitance are coupled to the ground terminal and to a second intermediate node;
• a supply line;
• a first precharging switch between the first main bitline and the supply line;
• a second precharging switch between the second main bitline and the supply line;
• a first local switch between the first local bitline and the first main bitline;
• a second local switch between the second local bitline and the second main bitline;
• a reading stage coupled to the memory array, the reading stage comprising a sense amplifier includes a first input terminal coupled to a first input terminal of the reading stage, a second input terminal coupled to a second input terminal of the reading stage, a first inverter having an input terminal coupled to the first input terminal of the sense amplifier and an output terminal coupled to the second input terminal of the sense amplifier, and a second inverter having an input terminal coupled to the second input terminal of the sense amplifier and an output terminal coupled to the first input terminal of the sense amplifier;
• and
• a first main-selection switch between the first input terminal and the first intermediate node;
• a second main-selection switch between the second input terminal and the second intermediate node;
• and
• a voltage comparator having a first comparison input coupled to the output terminal of the first inverter and a second comparison input coupled to the output terminal of the second inverter.