Shift register and display apparatus including the same
AssigneeLG Display Co., Ltd.
InventorsYongSeok PARK, Hyelim JI
Life of this patent
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Abstract
Provided are a shift register and display apparatus including the same. A shift register includes a plurality of stages, each of the plurality of stages including: a node controller configured to: periodically discharge a first node voltage generated from a first driving voltage during a first voltage level of a clock signal, and control a second node voltage opposite to the first node voltage based on a second driving voltage, and an output part configured to receive the clock signal to output an output signal based on the first node voltage.
Claims20
A shift register comprising a plurality of stages, each of the plurality of stages comprising:
- a node controller configured to:
- periodically discharge a first node voltage generated from a first driving voltage during a first voltage level of a clock signal;
- and
- control a second node voltage opposite to the first node voltage based on a second driving voltage;
- and
- an output part configured to receive the clock signal to output an output signal based on the first node voltage.
A display apparatus, comprising:
- a pixel array part comprising a plurality of pixels respectively provided in a plurality of areas defined by a plurality of scan lines and a plurality of data lines;
- a data driving circuit configured to supply a data signal to each of the plurality of data lines;
- and
- a scan driving circuit configured to supply a scan signal to each of the plurality of scan lines, the scan driving circuit comprising a shift register comprising a plurality of stages, each of the plurality of stages comprising:
- a node controller configured to:
- periodically discharge a first node voltage generated from a first driving voltage during a first voltage level of a clock signal;
- and
- control a second node voltage opposite to the first node voltage based on a second driving voltage;
- and
- an output part configured to receive the clock signal to output an output signal based on the first node voltage.
Dependencies are inferred from the claim text.