Reduced-power dynamic data circuits with wide-band energy recovery
AssigneeRezonent Corporation
InventorIGNATIUS BEZZAM
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Abstract
Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.
Claims18
A circuit system comprising:
- at least one sub-circuit in which at least one of the sub-circuits includes:
- a capacitive output node that is driven between low and high states in a random non-repetitive manner for a time period;
- an inductive circuit path coupled to the capacitive output node, the inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply;
- and
- a pulse generator circuit to generate a controlled input pulse width that corresponds to control the transistor switch and thus a timing for driving the capacitive output node.
A circuit system comprising:
- a first dynamic logic circuit forming at least one logic signal path and having a first switch and a first load capacitance to store and discharge electrical energy;
- a second dynamic logic circuit forming at least one logic signal path and having a second load capacitance to store and discharge electrical energy, the first and second load capacitances are connected electrically to form an aggregate load capacitance that is capable of discharging a fraction of the aggregate electrical energy;
- and
- a first inductor connected in series with the first switch and coupled to a first bias supply, the first inductor is configured to resonate with the aggregate load capacitance.
A digital logic driver comprising:
- a pull-down switch in series with an inductor, further connected in series with a reference supply;
- and
- a pull-up switch in series with the inductor, further connected in series with an energy saving adiabatic power supply, the inductor configured to enable the digital logic driver to resonate with a load capacitance of a capacitive output node.
A digital logic driver comprising:
- a first load capacitance;
- and
- a resonant inductor coupled to the first load capacitance, the resonant inductor has a reduced size due to being shared with multiple digital logic drivers, wherein the digital logic driver reuses electrical energy at several load capacitances including the first load capacitance and a second load capacitance, as part of a signal path of the digital logic driver without interfering with the signal path.
Dependencies are inferred from the claim text.