Processors, methods, and systems for debugging a configurable spatial accelerator

A method comprising:

• receiving an input of a dataflow graph comprising a plurality of nodes;
• overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements;
• performing an operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements;
• and
• entering, by at least a first of the plurality of processing elements, a halted state in response to being represented as a first of the plurality of dataflow operators.

A system comprising:

• a processor including:
• a plurality of processing elements;
• and
• an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as one of a plurality of dataflow operators in the plurality of processing elements, and the plurality of processing elements are to perform an operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements, wherein at least a first of the plurality of processing elements is to enter a halted state in response to being represented as a first of the plurality of dataflow operators;
• and
• a memory in which to store code to debug the processor, the code to include a first instruction having a first opcode, wherein the first of the plurality of processing elements is to be represented as the first of the plurality of dataflow operators by being configured to execute the first opcode.