Back to results
US 2019/0095363 A1Published application
High bandwidth link layer for coherent messages
AssigneeIntel Corporation
InventorsIshwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
Life of this patent
Estimating the term…
Abstract
Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
Claims25
An apparatus comprising:
- a memory device;
- a cache device;
- and
- a link layer component coupled to the memory device and the cache device, the link layer component to:
- identify first data received from the memory device, the first data of a first protocol format;
- identify second data received from the cache device, the second data of a second protocol format;
- and
- generate a flow control unit (flit) for transmission based on the first data and the second data, wherein the flit has a size of 528 bits.
5 more elements
A method comprising:
- identifying, by a link layer device, first data received in a first protocol format;
- identifying, by the link layer device, second data received in a second protocol format;
- multiplexing, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data;
- and
- generating, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
2 more elements
A system comprising:
- a transmitter device comprising:
- a memory for storing data,
- a cache for caching data,
- link layer logic implemented at least partially in hardware, and
- multiplexer logic implemented at least partially in hardware;
- a receiver device comprising:
- a decoder device to decode data packages received form the transmitter;
- wherein the link layer logic is to:
- identify, by a link layer device, first data received from the memory in a first protocol format;
- identify, by the link layer device, second data received from the cache in a second protocol format;
- multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data;
- and
- generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
10 more elements
Dependencies are inferred from the claim text.