Low-latency accelerator

A computer system, comprising:

• a multi-core processor, including:
• a plurality of processor cores, each processor core having at least one associated translation lookaside buffer (TLB), each TLB to store a plurality of TLB entries comprising a virtual address to physical address (VA-PA) translation;
• an interconnect fabric, communicatively coupled to each processor core and each TLB associated with each processor core;
• a memory controller, communicatively coupled to the interconnect fabric and having one or more memory channels;
• an input-output (TO) interface, communicatively coupled to the interconnect fabric;
• and
• an IOTLB to store a plurality of TLB entries comprising VA-PA translations for one or more IO devices;
• system memory comprising one or more memory devices, each communicatively coupled to at least one memory channel of the memory controller;
• a shared virtual memory (SVM)-capable accelerator having one or more functional units, either embedded on the processor or communicatively coupled to the processor via the IO interface;
• wherein the system is configured to,
• enqueue, on the accelerator via execution of an execution thread on one of the plurality of cores, a request descriptor for the accelerator, the request descriptor defining a job to be performed by the accelerator and including information associated with one or more buffers in system memory to be accessed by the accelerator during processing of the request descriptor;
• speculatively pre-fetch, via the accelerator, buffer data from the system memory though use of the information in the request descriptor associated with the one or more buffers;
• speculatively start processing of the job by processing at least a portion of the buffer data that is pre-fetched using one or more functional units of the accelerator;
• and
• verify whether or not the buffer data that is speculatively pre-fetched is the correct buffer data to be processed by the job.

A multi-core processor comprising:

• a plurality of processor cores, each processor core having at least one associated translation lookaside buffer (TLB), each TLB to store a plurality of TLB entries comprising a virtual address to physical address (VA-PA) translation;
• an interconnect fabric, communicatively coupled to each processor core and each TLB associated with each processor core;
• a memory controller, communicatively coupled to the interconnect fabric and having one or more memory channels;
• an accelerator, communicatively couple to the interconnect fabric, having one or more functional units and a request queue,
• wherein the multi-core processor is configured to be installed in a computer system including system memory comprising one or more memory devices coupled to the one or more memory channels when the processor is installed in the computer system, the computer system employing a shared virtual memory (SVM) architecture, and wherein each processor core has an instruction set architecture (ISA) including an instruction that upon execution, causes the processor to:
• enqueue a request descriptor in the accelerator request queue, the request descriptor defining a job to be performed by the accelerator and including an address hint for each of one or more buffers in system memory to be accessed by the accelerator during processing of the request descriptor,
• wherein the address hint for a buffer is to be employed by the processor to speculatively pre-fetch buffer data corresponding to the buffer from the system memory.