Techniques to provide debug trace information to a management host
AssigneeIntel Corporation
InventorsSHANKER RAMAN NAGESH, RAMAMURTHY KRITHIVAS, MANDIRA KUMAR SATHANANTHAM
Life of this patent
Estimating the term…
Abstract
Various embodiments are generally directed to an apparatus, method and other techniques to receive debug trace information via one or more pins, generate a packet comprising the debug trace information and a header, the header comprising header information to send the packet to a device coupled via one or more network connections, determine a location in a data buffer of an interface controller for the packet, and write the packet to the data buffer of the interface controller at the location.
Claims25
An apparatus, comprising:
- processing circuitry;
- and
- memory comprising one or more instructions, that when executed by the processing circuitry, to cause the processing circuitry to:
- receive debug trace information via one or more pins from a processor component;
- generate a packet comprising the debug trace information and a header, the header comprising header information to send the packet to a device accessible via one or more network connections;
- determine a location in a data buffer of an interface controller for the packet;
- and
- write the packet to the data buffer of the interface controller at the location.
A computer-implemented method, comprising:
- receiving debug trace information via one or more pins;
- generating a packet comprising the debug trace information and a header, the header comprising header information to send the packet to a device accessible via one or more network connections;
- determining a location in a data buffer of an interface controller for the packet;
- and
- writing the packet to the data buffer of the interface controller at the location.
A non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to:
- receive debug trace information via one or more pins;
- generate a packet comprising the debug trace information and a header, the header comprising header information to send the packet to a device accessible via one or more network connections;
- determine a location in a data buffer of an interface controller for the packet;
- and
- write the packet to the data buffer of the interface controller at the location.
Dependencies are inferred from the claim text.