Latency improvements between sub-blocks
AssigneeMicron Technology, Inc.
InventorParthasarathy Gajapathy
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first functional block. The first functional block includes one or more input buffers configured to receive signals, and one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block. The semiconductor device also includes a second functional block coupled to the first functional block. The second functional block includes a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block.
Claims18
A semiconductor device, comprising:
- a first functional block, comprising:
- one or more input buffers configured to receive signals;
- and
- one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block;
- and
- a command decoder coupled to the first functional block, comprising:
- a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block;
- and
- one or more flip-flops configured to receive decoded signals from the decode logic and output the decoded signals from the command decoder.
(canceled)
The semiconductor device of claim, wherein the one or more flip-flops of the command decoder are configured to be latched based on one or more clock signals.
A semiconductor device, comprising:
- a first functional block, comprising:
- logic configured to receive signals;
- and
- one or more flip-flops configured to latch the signals received by the logic and output the signals from the first functional block;
- and
- a second functional block coupled to the first functional block, comprising a decode logic configured to receive the signals output from the one or more flip-flops of the first functional block, wherein second functional block does not comprise flip-flops between the one or more flip-flops of the first functional block and the decode logic of the second functional block, and wherein the second functional block comprises one or more flip-flops configured to receive an output from the decode logic;
- wherein the one or more flip-flops of the first functional block and the one or more flip-flops of the second functional block are configured to be latched by identical clock signals.
(canceled)
16-21. (canceled)
Dependencies are inferred from the claim text.