Integrated circuit, ldmos with trapezoid jfet, bottom gate and ballast drift and fabrication method

A method to fabricate a laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising:

• implanting n-type dopants into a substrate to form an n-type buried layer (NBL) region in the substrate;
• implanting p-type dopants into the substrate to form a p-type buried layer (PBL) region above the NBL region;
• forming a drift region above the PBL region, including implanting n-type dopants into the substrate to form a first n-drift region portion above the PBL region, and implanting n-type dopants into the substrate to form a second n-drift region portion above and spaced from the first n-drift region portion to define a low doped gap drift region between the first n-drift region portion and the second n-drift region portion;
• forming an isolation structure extending downward through the second n-drift region portion and into the gap drift region portion, including a first end proximate a prospective drain region, and a second end under a prospective gate region;
• implanting p-type dopants into the substrate to form a p-body region extending through the drift region and into the PBL region to provide a channel region at a top surface of the substrate, the p-body region including a tapered side laterally spaced from the second end of the isolation structure by a first lateral distance at the top surface of the substrate and laterally spaced from the second end of the isolation structure by a smaller second lateral distance in the gap drift region portion;
• forming a gate structure extending over the channel region, the second n-drift region portion and a portion of the isolation structure;
• and
• implanting n-type dopants into the substrate to form an n-type source region adjacent the channel region in the p-body region, and an n-type drain region adjacent the first end of the isolation structure in the second n-drift region portion.

A laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising:

• a gate structure, including a gate dielectric layer formed over a substrate, and a gate electrode on the gate dielectric layer;
• a body region implanted in the substrate to provide a channel region under a portion of the gate dielectric layer
• a source region adjacent the channel region in the substrate;
• a drain region laterally spaced from a first side of the gate structure in the substrate;
• a drift region extending over a buried layer region in the substrate, the drift region including a first highly doped drift region portion above the buried layer region, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, the low doped gap drift region portion having a dopant concentration that is less than dopant concentrations of the first and second highly doped drift region portions;
• and
• an isolation structure, including a first end contacting the drain region, and a second end under the gate dielectric layer, the isolation structure extending downward through the second highly doped region portion and into the gap drift region portion.