Back to results
US 2019/0058034 A1Published application
Mos transistors in parallel
AssigneeSTMicroelectronics (Rousset) SAS
InventorFrançois Tailliet
Life of this patent
Estimating the term…
Abstract
An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.
Claims22
An electronic chip comprising:
- a plurality of first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected;
- a plurality of first isolating trenches, the first transistors being separated from one another by the first isolating trenches;
- a plurality of second transistors;
- and
- a plurality of second isolating trenches, the second transistors separated from one another by the second isolating trenches, wherein the first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.
2 more elements
An electronic chip comprising:
- a semiconductor substrate;
- a plurality of transistors connected in parallel so that gates of the transistors are interconnected, drain areas of the transistors are interconnected, and source areas of the transistors are interconnected, the drain areas and source areas being disposed in the semiconductor substrate;
- a plurality of small isolating trenches disposed in the semiconductor substrate so that the drain area of each of the transistors connected in parallel is separated from the drain area of another one of the transistors connected in parallel by a small isolating trench and so that the source area of each of the transistors connected in parallel is separated from the source area of another one of the transistors connected in parallel by a small isolating trench;
- a plurality of transistors that are not connected in parallel to any other transistor of the semiconductor substrate, each of the transistors that are not connected in parallel having a source area and a drain area disposed in the semiconductor substrate;
- and
- a plurality of large isolating trenches disposed in the semiconductor substrate adjacent source and drain areas of the plurality of transistors that are not connected in parallel, wherein each of the small isolating trenches has a width that is smaller than a width of any isolating trench adjacent a source area or a drain area of a transistor that is not connected in parallel.
3 more elements
An electronic chip comprising:
- a first transistor having a source area that is separated from a drain area by a channel area and also having a gate region overlying and insulated from the channel area, the source area, drain area and the channel area of the first transistor each having a first width;
- a second transistor having a source area that is separated from a drain area by a channel area and also having a gate region overlying and insulated from the channel area, the source area, drain area and the channel area of the second transistor each having a second width that is smaller than the first width;
- an isolating trench separating the source area of the first transistor from the source area of the second transistor, separating the drain area of the first transistor from the drain area of the second transistor, and separating the channel area of the first transistor from the channel area of the second transistor;
- and
- a plurality of small isolating trenches separating the source area, the drain area and the channel area of the first transistor into a plurality of regions, each small isolating trench having a width that is smaller than a width of the isolating trench.
2 more elements
An electronic chip comprising:
- a first transistor having a source area that is separated from a drain area by a channel area and also having a gate region overlying and insulated from the channel area, the source area, drain area and the channel area of the first transistor each having a first width;
- a second transistor having a source area that is separated from a drain area by a channel area and also having a gate region overlying and insulated from the channel area, the source area, drain area and the channel area of the second transistor each having a second width that is smaller than the first width;
- and
- an isolating trench separating the source area of the first transistor from the source area of the second transistor, separating the drain area of the first transistor from the drain area of the second transistor, and separating the channel area of the first transistor from the channel area of the second transistor;
- wherein the source area, the drain area and the channel area of the first transistor are divided into a plurality of areas that each have the second width.
2 more elements
Dependencies are inferred from the claim text.