US 2019/0057980 A1Published application

Active device array substrate

AssigneeAu Optronics Corporation

InventorsChih-Chung Su, Po-Hsueh Chen, Yi-Wei Chen, Hsiu-Chun Hsieh

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Abstract

An active device array substrate including a first scan line, a first data line, a second data line, a first active device, a first pixel electrode, a second active device, a second pixel electrode, and a first shielding pattern layer is provided. The first active device includes a first gate electrically connected to the first scan line, a first semiconductor pattern layer, a first source electrically connected to the first data line, and a first drain. The second active device includes a second gate electrically connected to the first scan line, a second semiconductor pattern layer, a second source electrically connected to the second data line, and a second drain. The first shielding pattern layer is overlapped with the first semiconductor pattern layer and the second semiconductor pattern layer. The first shielding pattern layer is overlapped with the second data line and not overlapped with the first data line.

Claims18

Dependent claims

An active device array substrate, comprising:

a first scan line;
a first data line;
a first active device, comprising:
a first gate includes two gate portions, wherein the two gate portions of the first gate respectively are two different portions corresponding to the first scan line;
a first semiconductor pattern layer including two channel portions, a source portion, a drain portion and a center portion, wherein the center portion is electrically connected between the two channel portions, wherein the source portion and the drain portion are at a same side of the first scan line, and wherein the center portion is located at another side of the first scan line;
and
a first source and a first drain electrically connected to the first semiconductor pattern layer, and the first source is electrically connected to the first data line;
a second active device, comprising:
a second gate electrically connected with the first scan line;
a second semiconductor pattern layer;
and
a second source and a second drain;
and
a shielding pattern layer substantially shielding the two gate portions of the first gate and the two channel portions of the first semiconductor pattern layer, wherein the source portion and the drain portion of the first semiconductor pattern layer are at a same side of the shielding pattern layer, and wherein the center portion of the first semiconductor pattern layer is located at another side of the shielding pattern layer.

11 more elements

An active array substrate, comprising a plurality of first repeating units and a plurality of second repeating units alternately arranged, wherein:

each of the first repeating units comprises:
a first scan line;
a first data line;
a first active device, comprising:
a first gate includes two gate portions, wherein the two gate portions of the first gate respectively are two different portions corresponding to the first scan line;
a first semiconductor pattern layer including two channel portions, a source portion, a drain portion and a center portion, wherein the center portion is electrically connected between the two channel portions, wherein the source portion and the drain portion are at a same side of the first scan line, and wherein the center portion is located at another side of the first scan line;
and
a first source and a first drain electrically connected to the first semiconductor pattern layer, and the first source is electrically connected to the first data line;
a second active device, comprising:
a second gate electrically connected with the first scan line;
a second semiconductor pattern layer;
and
a second source and a second drain;
and
a shielding pattern layer substantially shielding the two gate portions of the first gate and the two channel portions of the first semiconductor pattern layer, wherein the source portion and the drain portion of the first semiconductor pattern layer are at a same side of the shielding pattern layer, and wherein the center portion of the first semiconductor pattern layer is located at another side of the shielding pattern layer;
and
each of the second repeating units comprises:
an active device comprising a gate, a semiconductor pattern layer, a source and a drain;
and
another shielding pattern layer shielding at least a portion of the semiconductor pattern layer, wherein the another shielding pattern layer and the shielding pattern layer are disconnected with each other.

17 more elements

An active array substrate, comprising a plurality of first repeating units and a plurality of second repeating units alternately arranged, wherein:

each of the first repeating units comprises:
a first scan line;
a first data line;
a first active device, comprising:
a first gate includes two gate portions, wherein the two gate portions of the first gate respectively are two different portions corresponding to the first scan line;
a first semiconductor pattern layer including two channel portions, a source portion, a drain portion and a center portion, wherein the center portion is electrically connected between the two channel portions, wherein the source portion and the drain portion are at a same side of the first scan line, and wherein the center portion is located at another side of the first scan line;
and
a first source and a first drain electrically connected to the first semiconductor pattern layer, and the first source is electrically connected to the first data line;
a second active device, comprising:
a second gate electrically connected with the first scan line;
a second semiconductor pattern layer;
and
a second source and a second drain;
and
a shielding pattern layer shielding a portion of the first semiconductor pattern layer and a portion of the second semiconductor pattern layer;
and
each of the second repeating units comprises:
another data line;
an active device comprising a gate, a semiconductor pattern layer, a source and a drain, wherein the source is electrically connected with the another data line;
and
another shielding pattern layer shielding at least a portion of the semiconductor pattern layer, wherein the another shielding pattern layer and the shielding pattern layer are disconnected with each other.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/166,169Filed 22 Oct 2018
Priority: TW 1041287841 Sep 2015
Published: 21 Feb 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H10D 30/6723
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device: having…
H10D 86/421
Characterised by multiple TFTs: having a particular composition, shape or crystalline structure of the active layer
H10D 86/441
Characterised by multiple TFTs: interconnections, e.g. scanning lines

Family

Application15/099,613Division · filed 15 Apr 2016
Application16/166,169Division
US 10,128,273 B2Related patent
US 10,535,682 B2Related patent
US 2017/0062477 A1Published application
US 2019/0057980 A1This patent

From the US filing history. Foreign family members aren’t listed.

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