Semiconductor device and structure with thermal isolation

A semiconductor device, the device comprising:

• a first level of logic circuits, said logic circuits comprise a plurality of first transistors interconnected by a plurality of metal layers;
• a thermal isolation layer overlaying said first level;
• a second level of memory circuits, said memory circuits comprise an array of memory cells,
• wherein said second level is overlaying said thermal isolation layer;
• and
• connections from said logic circuits to said memory array comprising vias,
• wherein said vias have a diameter of less than 400 nm, and
• wherein said thermal isolation layer has a thickness of more than 400 nm and less than 4 microns.

A semiconductor device, the device comprising:

• a first level of logic circuits, said logic circuits comprise a plurality of first transistors interconnected by a plurality of metal layers;
• a thermal isolation layer overlaying said first level;
• a second level of memory circuits, said memory circuits comprise an array of memory cells,
• wherein said second level is overlaying said thermal isolation layer;
• and
• connections from said logic circuits to said memory array comprising vias,
• wherein said vias have a diameter of less than 400 nm, and
• wherein said device has an unpackaged size less than 0.5 mm for its horizontal or vertical sides.