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US 2019/0057904 A1Published application
Poly gate extension design methodology to improve cmos performance in dual stress liner process flow
AssigneeTexas Instruments Incorporated
InventorsYounsung Choi, Steven Lee Prins
Life of this patent
Estimating the term…
Abstract
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
Claims17
A method of forming an integrated circuit having a NMOS transistor and a PMOS transistor, comprising:
- forming a NMOS gate of the NMOS transistor that crosses opposite NMOS edges of a NMOS active area and extends past a first of the opposite NMOS edges nearest the PMOS transistor a first distance;
- forming a PMOS gate of the PMOS transistor that crosses opposite edges of a PMOS active area and extends past a first edge of the opposite PMOS edges nearest the NMOS transistor a second distance, wherein the first distance is greater than the second distance.
An integrated circuit having a NMOS transistor and a PMOS transistor, comprising:
- a NMOS gate of the NMOS transistor that crosses opposite NMOS edges of a NMOS active area and extends past a first of the opposite NMOS edges nearest the PMOS transistor a first distance;
- and
- a PMOS gate of the PMOS transistor that crosses opposite edges of a PMOS active area and extends past a first edge of the opposite PMOS edges nearest the NMOS transistor a second distance, wherein the first distance is greater than the second distance.
An integrated circuit, comprising:
- a first NMOS transistor with a first NMOS gate that crosses opposite NMOS edges of a first NMOS active area and extends past a first of the opposite NMOS edges a first distance;
- a second NMOS transistor having a second NMOS gate and second NMOS active area, the second NMOS transistor being located adjacent to the first NMOS transistor, wherein the first NMOS active area has a width that is smaller than the second NMOS active area and wherein the first NMOS gate has the same long side dimension as the second NMOS gate;
- a first PMOS transistor with a first PMOS gate that crosses opposite edges of a first PMOS active area and extends past a first edge of the opposite PMOS edges a second distance, wherein the first distance is greater than the second distance.
Dependencies are inferred from the claim text.