US 2019/0057903 A1Published application

3d semiconductor device and system

AssigneeMonolithic 3D Inc.

InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist

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Abstract

A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source.

Claims20

Dependent claims

A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal transistor;
a second level comprising second transistors;
a third level comprising third transistors;
a fourth level comprising fourth transistors,
wherein said first level is underneath said second level,
wherein said second level is underneath said third level, and
wherein said third level is underneath said fourth level;
at least a first metal layer and a second metal layer,
wherein said at least first metal layer and second metal layer comprise connections between a plurality of said first single crystal transistor;
and
NAND type memory cells,
wherein said NAND type memory cells comprise a plurality of said third transistors,
wherein a plurality of said fourth transistors are aligned to said plurality of said first single crystal transistor with less than 140 nm alignment error,
wherein said second metal layer is above said first metal layer,
wherein said first metal layer comprises a first current carrying capacity,
wherein said second metal layer comprises a second current carrying capacity,
wherein said first current carrying capacity is significantly greater than said second current carrying capacity,
wherein said third transistors are junction-less transistors (JLT),
wherein each of said fourth transistors comprise a transistor channel, a drain and a source, and
wherein said transistor channel is significantly narrower than said drain or said source.

17 more elements

A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal transistor;
a second level comprising second transistors;
a third level comprising third transistors;
a fourth level comprising fourth transistors,
wherein said first level is underneath said second level,
wherein said second level is underneath said third level, and
wherein said third level is underneath said fourth level;
at least a first metal layer and a second metal layer,
wherein said at least first metal layer and second metal layer comprise connections between a plurality of said first single crystal transistor;
and
wherein a plurality of said fourth transistors are aligned to said plurality of said first single crystal transistor with less than 140 nm alignment error,
wherein said second metal layer is above said first metal layer,
wherein said first metal layer comprises a first current carrying capacity,
wherein said second metal layer comprises a second current carrying capacity,
wherein said first current carrying capacity is significantly greater than said second current carrying capacity,
wherein said third transistors are junction-less transistors (JLT),
wherein each of said fourth transistors comprise a transistor channel, a drain and a source, and
wherein said transistor channel is significantly narrower than said drain or said source.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/166,636Filed 22 Oct 2018
Priority: US PCT/US2011/04207128 Jun 2011
Published: 21 Feb 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification86 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 11/005
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor: comprising combined but…

Family

Application13/635,436Continuation · filed 16 Sep 2012
Application13/623,756Continuation in part · filed 20 Sep 2012
Application14/975,830Continuation in part · filed 20 Dec 2015
Application15/488,514Continuation in part · filed 16 Apr 2017
Application15/904,347Continuation in part · filed 24 Feb 2018
Application16/043,133Continuation in part · filed 23 Jul 2018
Application16/166,636Continuation in part
Application13/623,756Continuation
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